
`define USE_YOSYS
`ifdef USE_YOSYS
(* blackbox *)
module cycloneive_clkctrl(
    ena,
	inclk,
	clkselect,
	devclrn,
	devpor,
	outclk
    );
	input wire ena;
	input wire[3:0] inclk;
	input wire[1:0] clkselect;
	input tri devclrn;
	input tri devpor;
	output wire outclk;
endmodule

module def_clk (
    clk_in,
    clk_out
);
    input wire clk_in;
    output wire clk_out;



    tri devclrn;
    tri devpor;
    tri devoe;
    wire outclk;
    // Location: CLKCTRL_G2
cycloneive_clkctrl inputclkctrl (
	.ena(1'b1),
	.inclk({1'b1,1'b1,1'b1,clk_in }),
	.clkselect(2'b00),
	.devclrn(devclrn),
	.devpor(devpor),
	.outclk(outclk ));
// synopsys translate_off
defparam inputclkctrl .clock_type = "global clock";
defparam inputclkctrl .ena_register_mode = "none";
// synopsys translate_on


    assign clk_out = outclk;
endmodule

`else
module def_clk (
    clk_in,
    clk_out
);
    input wire clk_in;
    output wire clk_out;
    assign clk_out = clk_in;
endmodule
`endif


/*定义rv32黑盒*/
(* blackbox *)
module alta_rv32 (
  input         sys_clk,
  output        mem_ahb_hready,
  input         mem_ahb_hreadyout,
  output [1:0]  mem_ahb_htrans,
  output [2:0]  mem_ahb_hsize,
  output [2:0]  mem_ahb_hburst,
  output        mem_ahb_hwrite,
  output [31:0] mem_ahb_haddr,
  output [31:0] mem_ahb_hwdata,
  input         mem_ahb_hresp,
  input  [31:0] mem_ahb_hrdata,
  input         slave_ahb_hsel,
  input         slave_ahb_hready,
  output        slave_ahb_hreadyout,
  input  [1:0]  slave_ahb_htrans,
  input  [2:0]  slave_ahb_hsize,
  input  [2:0]  slave_ahb_hburst,
  input         slave_ahb_hwrite,
  input  [31:0] slave_ahb_haddr,
  input  [31:0] slave_ahb_hwdata,
  output        slave_ahb_hresp,
  output [31:0] slave_ahb_hrdata,
  input  [7:0]  gpio0_io_in,
  output [7:0]  gpio0_io_out_data,
  output [7:0]  gpio0_io_out_en,
  input  [7:0]  gpio1_io_in,
  output [7:0]  gpio1_io_out_data,
  output [7:0]  gpio1_io_out_en,
  output [1:0]  sys_ctrl_clkSource,
  output        sys_ctrl_hseEnable,
  output        sys_ctrl_hseBypass,
  output        sys_ctrl_pllEnable,
  input         sys_ctrl_pllReady,
  output        sys_ctrl_sleep,
  output        sys_ctrl_stop,
  output        sys_ctrl_standby,
  input  [7:0]  gpio2_io_in,
  output [7:0]  gpio2_io_out_data,
  output [7:0]  gpio2_io_out_en,
  input  [7:0]  gpio3_io_in,
  output [7:0]  gpio3_io_out_data,
  output [7:0]  gpio3_io_out_en,
  input  [7:0]  gpio4_io_in,
  output [7:0]  gpio4_io_out_data,
  output [7:0]  gpio4_io_out_en,
  input  [7:0]  gpio5_io_in,
  output [7:0]  gpio5_io_out_data,
  output [7:0]  gpio5_io_out_en,
  input  [7:0]  gpio6_io_in,
  output [7:0]  gpio6_io_out_data,
  output [7:0]  gpio6_io_out_en,
  input  [7:0]  gpio7_io_in,
  output [7:0]  gpio7_io_out_data,
  output [7:0]  gpio7_io_out_en,
  input  [7:0]  gpio8_io_in,
  output [7:0]  gpio8_io_out_data,
  output [7:0]  gpio8_io_out_en,
  input  [7:0]  gpio9_io_in,
  output [7:0]  gpio9_io_out_data,
  output [7:0]  gpio9_io_out_en,
  input         ext_resetn,
  output        resetn_out,
  output        dmactive,
  output        swj_JTAGNSW,
  output [3:0]  swj_JTAGSTATE,
  output [3:0]  swj_JTAGIR,
  input  [7:0]  ext_int,
  input  [3:0]  ext_dma_DMACBREQ,
  input  [3:0]  ext_dma_DMACLBREQ,
  input  [3:0]  ext_dma_DMACSREQ,
  input  [3:0]  ext_dma_DMACLSREQ,
  output [3:0]  ext_dma_DMACCLR,
  output [3:0]  ext_dma_DMACTC,
  input  [3:0]  local_int,
  input  [1:0]  test_mode,
  input         usb0_xcvr_clk,
  input         usb0_id
);

endmodule

module gpio (
    clk,
    ledout,
    gpio_pin
);
    input wire          clk;
    output wire[3:0]     ledout;
    output wire[3:0]     gpio_pin;

    wire[7:0] gpio4_io_out_en;
    assign ledout = gpio4_io_out_en[3:0];
    assign gpio_pin[1] = gpio_pin_out[0];

    wire [7:0] gpio_pin_out;

    alta_rv32 rv32(
		.sys_clk(1'b0),
        .gpio4_io_in(8'b01010101),
        .gpio4_io_out_data(gpio_pin_out),
        .gpio4_io_out_en(gpio4_io_out_en)
		  /*

        .gpio4_io_out_en(gpio_pin_out_en),
		  .mem_ahb_haddr(mem_ahb_haddr),
		  .sys_ctrl_clkSource(sys_ctrl_clkSource),

		  .mem_ahb_hreadyout(1'b1),
		  .slave_ahb_hready(1'b1),

			.mem_ahb_hresp(1'b0),
			.mem_ahb_hrdata(32'h0),
			.slave_ahb_hsel(1'b0),
			.slave_ahb_htrans(2'b0),
			.slave_ahb_hsize(3'b0),
			.slave_ahb_hburst(3'b0),
			.slave_ahb_hwrite(1'b0),
			.slave_ahb_haddr(32'b0),
			.slave_ahb_hwdata(32'b0),
			.sys_ctrl_pllReady(1'b0),
			.ext_resetn(1'b0),
			.ext_int(8'b0),
			.ext_dma_DMACBREQ(4'b0),
			.ext_dma_DMACLBREQ(4'b0),
			.ext_dma_DMACSREQ(4'b0),
			.ext_dma_DMACLSREQ(4'b0),
			.local_int(4'b0),
			.test_mode(2'b0),
			.usb0_xcvr_clk(1'b0),
			.usb0_id(1'b0),
			*/
    );


endmodule